Who builds the brains? The Sundai Hack 145 chip panel, explained simply

AI can already help design chips. The harder questions are who can build them, how fast, and what they should be built to do.

The whole panel in 30 seconds

The two hosts of Sundai Hack 145 spent an hour at MIT CSAIL in October 2026 talking about where AI meets chip design, chip factories and data centers. Their main argument: AI is about to make designing chips much faster, but manufacturing them is the slow part, so that is where the real bottleneck sits. Around that core, they argued about memory, energy, what a data center should optimize for, and who ends up making money.

I was in the room. Below, each idea starts with a simple picture, then what the hosts said, then what the research found. Where the two disagree, there is a "Fact check" box. At the end, a "Follow the money" section adds what The Economist reported about AI funding in the weeks around the panel.

5 big ideas

There are 5 topics. Topic 1 has 5 points, topic 2 has 4, topic 3 has 4, topic 4 has 5, and topic 5 has 4.

  1. AI is learning to design chips.
  2. The factory, not the design, is the wall.
  3. Custom chips win because moving data is expensive.
  4. "Fast" depends on the job.
  5. The money, the cycles, and the split into specialist chips.

1. AI is learning to design chips

Imagine a spelling test that comes with an answer key. A computer can grade its own answers, so it can practice a million times without a teacher. Chip design has an answer key too: a simulator tells you whether the circuit works. That makes it a great thing for AI to practice on.

From idea to chip: where verification takes the time Chip design runs from spec to RTL, verification, physical design, tape-out and fab; verification is the biggest stage at about half of project time (53 percent in the 2018 Wilson Research study), and AI agents are arriving at RTL, verification and physical design. From idea to chip Spec RTL Verification about half of project time 53% (Wilson Research, 2018) Physical design Tape-out Fab AI agents AI agents AI agents RTL: the circuit written as code. Verification: testing it before it is built. Tape-out: sending the finished design to the factory (the fab). AI agents: software helpers that are starting to show up in these steps.

What the hosts said

What the research says

Fact check: Two gentle corrections. First, the 70% figure is folklore. The researcher behind the best-known industry survey wrote that the number opens nearly every verification paper but has no traceable source; his surveys found 50% in 2007 and 55% in 2010 (Siemens, Apr 2011). The latest figure I could check is 53% of project time in 2018 (Siemens, Jan 2019). So "about half" is right and "about 70%" is not. Second, the chip-in-a-week story: research found no public record of it, with no post, vendor or shuttle named. What is public is that Anthropic hired in July 2026 for a Chip Design RL role that builds AI training setups for chip design and verification (Anthropic job post, Jul 2026). That points the same direction as the story, but it does not prove it. Treat the story as unverified. Third, the prediction that chip design could be "almost solved" in three or four years is more optimistic than the survey, which sees autonomous flows only for single blocks in 3 to 5 years.

Why it connects

If AI makes design fast, the next question is whether anyone can manufacture all those new designs, which is topic 2.

2. The factory, not the design, is the wall

A chip design is a recipe, and a chip factory is a giant kitchen with one very expensive oven. AI can write a thousand recipes overnight. But the oven takes ages to learn, and the kitchen can only cook so much. More recipes do not help if the oven is the slow part.

The wall between chip designers and the fab Chip designers (NVIDIA, Google, OpenAI with Broadcom) sit on one side of a wall, the TSMC foundry on the other, and ASML tool makers feed the fab; a design must cross the wall and then wait years for the fab to calibrate. Designers on one side, the factory on the other the wall feed the fab Chip designers NVIDIA Google OpenAI with Broadcom Foundry: TSMC Years to calibrate Tool makers: ASML EUV machine: about $180M High-NA machine: about $380-400M Envelope = the finished chip design. It crosses the wall, then waits.

What the hosts said

Amdahl's law: speed up the short step and the total barely moves Two bars of time to a new chip, design then manufacturing; when the design segment shrinks a lot, the manufacturing segment stays the same, so the total is only slightly shorter. Speed up the short step, the total barely moves Before Design Making the chip (the fab) Total: a long wait After Making the chip (the fab) Design (much faster) Total: almost the same dashed line = the old total

What the research says

Fact check: "400 million per machine" is a High-NA price. The previous-generation (lower-NA) machines were about $180 million in the same 2024 report, and a current price for those machines was not confirmed (eeNews Europe, Mar 2024). The research also could not confirm the "year and a half to two years" calibration time or the cost of TSMC pausing to experiment. They may be true inside the industry; they are just not on the public record.

Why it connects

If the factory is the slow step, every chip that does get made needs to count, which is why topic 3 is about squeezing more out of each one.

3. Custom chips win because moving data is expensive

A chef can chop vegetables in a blink, but the fridge is down the street. Most of the time and energy goes into walking to the fridge, not cooking. Custom chips put the groceries on the counter, or build the recipe into the kitchen itself, so you stop walking.

The memory wall: adding is cheap, fetching is not On a log scale, an 8-bit add costs 0.03 pJ and a 32-bit add 0.1 pJ, while a DRAM access costs 1.3 to 2.6 nJ and runs off the chart; below, a spectrum from flexible CPU and GPU to TPU to hardwired chips such as Taalas. Adding is cheap. Fetching from memory is not. 0.1 pJ 1 pJ 10 pJ Each gridline is ten times the one before (log scale) 8-bit add 0.03 pJ 32-bit add 0.1 pJ Fetch from DRAM 1.3 to 2.6 nJ per fetch, off the chart Flexible or fast: pick your point CPU GPU TPU Hardwired (Taalas) most flexible fastest, but fixed Energy numbers: Horowitz, ISSCC 2014 (45nm chips).

What the hosts said

What the research says

Fact check: On memory, the host if anything undersold it. For a bare 32-bit add, the 2014 table implies a DRAM access costs roughly 10,000 times more or higher, though "about a thousand" is the right order of magnitude (Horowitz, Feb 2014). On the OpenAI chip, the research could not trace the 120 versus 700 tokens per second (7x) comparison to a published source, and OpenAI gave no speed figure at launch (DBTA, Jun 2026). Treat the 7x as unverified.

Why it connects

Once you can make a chip faster or cheaper, you have to decide which of those you actually want, which is topic 4.

4. "Fast" depends on the job

Think of a printer. Tokens per second is how fast pages come out, and cost per token is the price of ink. Some people pay extra for express printing; others are happy to wait. And a printer on the Moon mostly just needs to survive.

What the hosts said

What the research says

Fact check: ARC's benchmark is not quite half open, half closed. ARC-AGI-2 has 120 public evaluation tasks and 240 hidden ones (120 semi-private plus 120 private), so hidden tasks outnumber public ones two to one (ARC Prize, fetched Oct 2026). The spirit of the point holds: keep part of the test secret.

Why it connects

What you optimize for decides what gets built and who pays for it, which brings us to the money in topic 5.

5. The money, the cycles, and the split into specialist chips

When every lemonade stand sees lemons selling out, they all plant lemon trees. Years later the trees ripen at once, there are too many lemons, and prices crash. Chip factories take years to build, so they often get the timing wrong in the same way.

One chip becomes two, and compute moves out Google's eighth-generation TPU is two chips, TPU 8t for training and TPU 8i for inference, and NVIDIA's Rubin CPX is another workload-specific chip; compute is spreading from hyperscale campuses to the edge and to orbit (Suncatcher, Starcloud). One chip becomes two TPU 8t for training (learning) TPU 8i for inference (answering fast) NVIDIA's Rubin CPX is a second example: a chip just for very long inputs. And the compute is moving out Hyperscale campus giant data centers Edge small, near the user Orbit Suncatcher, Starcloud

What the hosts said

What the research says

Fact check: The cycle is real, but the research does not confirm "4 to 6 years." One analysis says past memory supercycles tended to peak and turn down within one or two years, while calling this one larger and longer than usual (SemiAnalysis, Feb 2026). And for now Amazon's CEO says capacity will still fall short of demand in 2026 and 2027, not that it is overbuilt (Fortune, Jul 2026).

Why it connects

Money flowing into AI, from data-center spending to startup funding like ChipAgents, is part of what drives topic 1's AI design tools, which closes the loop. And in the weeks after the panel, the money itself became the story.

Follow the money: what happened after the panel

Picture a toy shop that sells so many toys it starts lending kids the money to buy them. Business looks amazing, as long as the kids keep wanting toys. If they get bored, the shop is stuck holding the loans. That is roughly where AI money stood in the fall of 2026.

The hosts warned about boom-and-bust cycles. Over September and October 2026, The Economist ran a string of stories showing just how big the bet has become, and where it could crack. Here are the 4 things worth knowing.

1. The chipmaker became the bank

2. The build-out now runs on debt

3. The revenue has not caught up yet

4. Data centers are physical, and that brings physical risk

How this ties back to the panel: The hosts predicted a cycle, said the cloud giants are moving data centers off their books, and argued the factory is the slow step. All three show up in the money. The cycle risk is now priced into bonds, the off-book structures have grown to trillions, and every dollar of new demand still has to squeeze through a handful of factories.

What the teams built the same weekend

The panel was the cooking class. The hackathon was the kitchen. Right after hearing about walls, memory and money, teams went off and tried to build the thing themselves, and they ran into the very same limits.

Sundai Hack 145 had two tracks. Track 1 asked teams to build the AI data center of 2035 on a $30 billion budget over 5 years, with only 500 MW of grid power across all sites, launch at $200 per kilogram, and answers that start within 0.6 s for chat and 2 s for agents (Orbital Data Center README). Track 2 asked teams to design the coolest chiplet layout for a simulated GPU and memory package (Supah Silicon README). Here are 6 public projects, including my own, and the panel idea each one puts to the test.

What the builds show: The three Track 1 teams that published numbers all ran into the same limit, and it was power, not chips: the orbital team's grid filled up, the quantum team's GPU option broke the 500 MW cap, and the campus team used 499.70 of its 500 MW. That is the hosts' Amdahl's law point in action: the build is only as fast as its slowest step, and for a 2035 data center the slowest step is getting enough electricity.

How the 5 ideas fit together

The five ideas as one loop A loop of five steps: money (capex) pays for chips designed with AI, which hit the manufacturing wall, then memory and energy limits, which shape what we optimize for (tokens per second, cost per task), which decides where the money goes next. Five ideas, one loop What we optimize for decides where the money goes next 1 Money (capex) build-out spending 2 Chips designed with AI helping 3 Manufacturing wall few fabs, slow to change 4 Memory and energy moving data costs most 5 What we optimize tokens per second, cost per task

Read the five topics as one loop. Money (capex) funds new chips. AI makes designing them faster. The factory wall limits how many get made. Memory and energy limits decide what a good chip looks like. And the choice of what to optimize, tokens per second or cost per task, decides what buyers will pay for, which sends money back to the start.

The hosts' sharpest point is Amdahl's law applied to design versus manufacturing. Faster design is exciting, but the whole process only moves as fast as its slowest link, and today that link is manufacturing.

Words to know

How this was made

I recorded the panel on my phone and transcribed it locally with Whisper. Five research lanes then checked the hosts' claims against public sources, and two adversarial fact-checkers tried to knock each finding down. Of 40 claims checked, 0 were killed and 24 were corrected, and key numbers were re-checked against the source pages wherever the pages could be fetched. Vendor and aggregator figures are flagged as such. Every fact from the panel research comes from the verified fact sheet: research/facts.md. The Economist facts were read in full from 11 subscriber articles published between August 30 and October 18, 2026, and each one links to its article. The team projects are described from their public GitHub READMEs (research/hack_projects.md); their numbers are the teams' own simulations, not independent checks. The hosts are not named because their names are unconfirmed. If you spot an error, I would like to know.